Monash University > School of Computer Science and Software Engineering > CSE1303 > Part B > Lectures > Lecture B08 notes

CSE1303 Computer Science
Semester 3 (summer), 2003
Part B
Lecture B08 notes: The MIPS computer architecture

In this lecture

• MIPS architecture
  • Microprocessor (CPU)
  • Coprocessor 0 (memory management and exceptions)
  • Coprocessor 1 (floating point)
  • Main memory
• Registers
  • Fast memory located on CPU
  • 32 x 32-bit general-purpose registers ($0 to $31)
    • Also given names, e.g., $0, $ra, $t2, $sp
  • Special-purpose registers: PC, LO, HI
• Execution: fetch-execute cycle
• Memory organization
  • 32-bit addresses
  • Only loads and stores can access memory
  • Segments
    • Text segment: for machine language code
    • Data segment: for static data
      • includes heap (for dynamic memory)
    • Stack segment: for temporary storage
• SPIM simulator

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Last modified 2002-12-05