Images

Below are some images taken throughout the year.  


 


This is a photo showing how the bus system on the Gameboy was interrogated using the logic analyser.

probes



This is a sample analysis of the Gameboy bus operating. The sample was taken using the HP logic analyser.

bus analysis



This is the complete schematic in DesignView.

schematic



This is a simulation of the UART receiver and shift register in VHDL. The simulation was carried out using Vsim.

simulation


Last modified November 15th 2004
Brett Carter. 18151515