March

Working on Research Proposal 

At this stage I have to decide on what direction I would like to take this project.  Chris Elliott, an honours student from 2003, started this project and focused mainly on the network configuration of the wireless sensor nodes.  His web page can be found here: Chris Elliott's Web Page

I will be looking at the remote reconfiguration of an FPGA interfaced directly to an Ad Hoc sensor.  This well need to be done while the system is active, also known as Live Reconfiguration. 

April

Completed Research Proposal: Download Here (PDF)

Have spent a lot of time reading over this month but have found minimal information so far relevant to my research. Currently following some leads based on what Xilinx calls "IRL" or "Internet Reconfigurable Logic".

I am hoping to find information on methods used or problems found when FPGA's are reconfigured while embedded in an active system. Some kind of a protocol describing how the FPGA can be shut down and reconfigured while the rest of the system is still running.

At the University of Hawaii, a project was undertaken that involved the reconfiguration of an FPGA over the internet connected via an Ethernet link.  This project had similar goals to this current project but did not involve an existing system that the FPGA would be 'piggy-backed' on.  The FPGA was connected directly to the Ethernet link with specificaly designed software and hardware.  The Ad Hoc sensor motes that will be utilised in this project were not specifically designed for the reconfiguration of PLDs.

May

If you would like a nice overview of what I am working on, my Interim Presentation will give you a firm grasp of my topic.

Interim Presentation: Download Here (Power Point)

Currently researching JTAG for programming FPGA's.  I have access to a Virtex chip on an interface card as well as a Spartan 2 digilab board which can be seen in the pictures section of this website.  Plans to connect an Atmel Atmega processor to this board and have it program the Virtex or spartan chip are currently in the works.  Using a program called Expedition to create a PCB for the Atmel to sit on as well as learning how to use the JTAG port directly.

Literature Review under way. 

June

HOLIDAYS!

Yes, I have been coming to uni over the holidays.  Spent most of my time learning how to use Mentor Graphics software such as Expedition PCB for creating Printed Circuit Boards that I will be making as prototypes for this project.  For each PCB that is made, there is a lot of setup work that needs to be done before hand such as creating Symbols, Cells and parts, designing the schematic in design view and creating the layout in expedition using routing tools.

Had some trouble setting up the parts libraries included with the software.  The problem was not with the library but rather with the parts not having been included in the design.  Each part must be included in the design schematic before it can be placed in the routing software.

Parts that were not in the library had to be created using the Library Manager.  From this application it is possible to launch other design applications such as Symbol Editor for creating the design symbols, Cell Editor for generating the physical layout of the part on the PCB and Part Editor for linking each Symbol to the correct Cell.

July

Literature Review: Download Here (PDF)

Finding lots of useful information in Xilinx Application notes more than in research papers.  JTAG reconfiguration is different for each Spartan.  New chips have instructions for startup and old chips require that you do lots a manual clocking of bits rather than using simple instructions.  For the Spartan-xcs10 XL being used, fifteen zeros need to be added to the end of the bit stream and the EXTEST instruction also needs to be executed.

Found a company that sells Hirose Bus connectors that I need to interface my prototype to the actual sensor nodes that are being purchased from Davidson, distributors for Crossbow in Australia.  Used the data sheet to create the symbol and cell in expedition and ran a test board to ensure measurements and to see if it was big enough to solder by hand.  Turns out that I'm going to have to use solder paste.

August

Lots of coding this month.  Creating interface software between the TOSSIM simulator and the parallel port so that I am able to talk to the FPGA on the digilab board.  Using this program will let me test the software that will be running on the sensor mote as if it was connected to the FPGA, especially useful because we don't have the hardware yet. 

Created the first prototype that can be used for testing.  The prototype had header pins that were able to connect to the parallel port through the Xilinx Xchecker cable.  The interface code translates the actions during simulation into suitable signals for the Xchecker.  Configuratoin of the spartan 2 on the digilab board required a lot of fine tuning.  Learnt that there is a startup procedure involved when configuring FPGA's over JTAG.

Moving onto testing the Spartan XL, the FPGA that is being used on the final design. 

The data sheet for the XL describes a sequence that must be followed for configuration.  This is totally wrong.  Spent hours trying to make it work but there was no sign of life.

Study of iMPACT shows that this is clearly not how configuration occurs.  Investigating other approaches to reconfiguration.

September

Sensor mote arrived!  It took a while to get the wireless communication happening between the motes as the software that we had was not setup properly.  It required that you set the intended frequency before you compile and download any code to the motes.  Information about the format of the configuration file is in the tutorial and help documentation that comes with the software, just takes a bit of digging to find it. 

Tested software on the motes that would act as the JTAG programmer for the FPGA to make sure the design was correct for the prototype which needed the correct pins on the bus connector being used to interface to the mote. 

SVF files produced from iMPACT show methods for configuration of FPGA's that were successful in reconfiguration the chip unlike those given in the data sheet.

Developing Java software to grab the reconfiguration data and send it over the wireless between the base station and the node with the FPGA attached. 

October

Problems with the Java software that forwards packets to the serial forwarder.  The program can only handle about 700 packets before the overflows.  This problem can be fixed as it exists in the java that I wrote. 

Writing the Thesis 

November

Thesis (PDF) handed in!!

THE END!