i have started to attempt the sample exam questions available on your websites.

there is something i dun understand for question 1,

that is what do u mean by hardware interlocking, what difference does it

made to the timing

diagram for a set of instructions, i cannot find the definition or

explanation for it in

lecture notes and in the text, that is why i wrote this email to u hoping

u can help me in clarifying

this term. Thanks for the time taken to read this email.

Interlocking hardware is the hardware that blocks the pipeline when dependencies are detected. Show what happens when it is present and not, i.e. when the pipeline stalls automatically and when it doesn't

What does orthogonal mean with regards to RISC arch.?

It means that the same techniques are used for all instructions, the address and register fields are found in the same bit positions in all instructions, etc. The opposite is to have different encodings for various instructions, like other CISC machines.